Introduction

About this specification

This document is the authoritative specification of the PicoLink cache-coherency protocol and of the PicoLink verification IP that implements it. It defines the message set, message field formats, signal-level transport, the coherence state machine observed at each core, the required behavior of the Coherency Manager, and the resolution of all architecturally visible race conditions.

The intended audience is:

  • Designers implementing a PicoLink requester (core-side L1/L2 controller) or a PicoLink Coherency Manager.

  • Verification engineers writing stimulus, checkers, and coverage against this protocol.

Release information

Issue

Date

Change summary

0.1

2026

Initial draft: message set, MESI transitions, basic CM behavior.

0.2

2026-07-03

Normative rewrite. Added numbered protocol rules, signal-level transport chapter, transaction-identifier allocation rules, channel dependency (deadlock-avoidance) rules, forward-progress guarantees, and complete race enumeration. Corrected the E-holder invalidation behavior and the ReadShared/Upgrade race description.

Document conventions

Normative language

The key words below are used with the following meanings:

Key Word

Meaning

shall / shall not

A mandatory requirement. Non-compliance makes an implementation non-conformant.

should

A recommendation. Deviations are permitted but must be justified.

may

A permitted behavior or implementation choice.

can

A statement of capability or possibility, not a requirement.

Rule identifiers

Normative requirements are tagged with unique identifiers of the form PL-<AREA>-<NN>, for example PL-ORD-01. These identifiers are stable across releases and are intended to be referenced from testbenches, checkers, and compliance reports. The areas are:

Area

Scope

PL-CHAN

Channel and message-usage rules.

PL-SIG

Signal-level handshake and reset rules.

PL-FLD

Message field content rules.

PL-TXN

Transaction-identifier allocation and matching rules.

PL-MESI

Requester (core-side) coherence state rules.

PL-CM

Coherency Manager behavior rules.

PL-ORD

Message ordering rules.

PL-DEP

Channel dependency and deadlock-avoidance rules.

PL-RACE

Race resolution rules.

PL-PROG

Forward-progress guarantees.

Numbering and units

  • Numeric constants prefixed with 0x are hexadecimal; all other constants are decimal.

  • Bit 0 is the least-significant bit of any field.

  • A cache line is the unit of coherence. The default line size is 64 bytes; see Message Field Definitions for the parameter definitions.

Protocol overview

PicoLink is a directory-based cache-coherency protocol derived from TileLink, with a deliberately reduced message set intended for small multi-core systems and for protocol-verification training environments. Its defining properties are:

  • MESI (Modified, Exclusive, Shared, Invalid) coherence model at each requester.

  • Exactly two channels: A (Core → CM) and B (CM → Core). See Channels.

  • No probe/downgrade messages. The only demand the Coherency Manager can make of a core is full invalidation (Invalidate). A core holding a line in E or M can never be downgraded to S; it can only be invalidated.

  • No Release handshake. Clean lines (S, E) are evicted silently, without notifying the Coherency Manager.

  • No cache-to-cache transfers. Memory is the only source of granted data: the data payload of every GrantS and GrantE is supplied from memory, never forwarded from another core’s cache.

System architecture

        flowchart LR
    subgraph Cores
        C0["Core 0 + private L1"]
        C1["Core 1 + private L1"]
        CN["Core N-1 + private L1"]
    end
    CM["Coherency Manager<br/>(directory)"]
    MEM["Memory<br/>(clean data only)"]

    C0 <-- "A / B" --> CM
    C1 <-- "A / B" --> CM
    CN <-- "A / B" --> CM
    CM <--> MEM

The protocol assumes the following system architecture:

  • Each CPU core has its own private L1 cache; there are no shared caches between the cores and the Coherency Manager.

  • A single, central Coherency Manager (CM) owns the directory. It tracks, per cache line, which cores hold copies and in what state, and it is the serialization point for all coherence decisions (see Coherency Manager (CM) Behavior).

  • Memory stores only clean data. Dirty data exists only in a core’s L1 in M state, or in flight in a WriteBack message. The CM commits every received WriteBack payload to memory before granting the line to another core.

  • Each core is connected to the CM by one independent pair of A/B channels (a point-to-point topology from the protocol’s perspective; the physical interconnect is implementation defined).

Scope and limitations

The following are out of scope for this specification:

  • Uncached or device (I/O) accesses — all PicoLink traffic is cacheable and cache-line sized.

  • Sub-line transfers, byte enables, and partial writes.

  • Multiple Coherency Managers, address interleaving, and multi-level directories.

  • Virtual memory and address translation — all addresses are physical.

  • Error signaling, poisoning, and RAS features — PicoLink has no error response; Nack is a race-resolution mechanism, not an error indication.

  • Atomic (read-modify-write) bus operations — cores implement atomics using exclusive ownership (E/M) locally.