Glossary

Cache line

The unit of coherence and of data transfer. Default 64 bytes. All PicoLink addresses are line-aligned (PL-FLD-02).

CM

Coherency Manager: the central directory-based controller that tracks cache-line ownership and sharing, and serializes all coherence transactions (see Coherency Manager (CM) Behavior).

Demand

A CM-initiated message requiring core action. Invalidate is the only demand in PicoLink.

Directory

The CM-maintained structure mapping each cache line to its state, sharer set, and owner (see Coherency Manager (CM) Behavior).

E (Exclusive)

Line is clean and held exclusively by one core; memory also holds current data. A store promotes it to M silently.

Exclusive-grant optimization

Responding to ReadShared with GrantE when the requester becomes the sole holder (PL-CHAN-06), allowing a later store without an Upgrade.

Forced WriteBack

A WriteBack a core sends in response to Invalidate, echoing the Invalidate’s CM-pool txn_id (PL-TXN-04). The CM classifies forced versus voluntary by outstanding-Invalidate state, not by txn_id value (PL-TXN-05).

Grant

A CM response conferring permission on a line: GrantS (Shared, with data), GrantE (Exclusive, with data), or GrantM (Modified, no data).

I (Invalid)

Line is not present in the core’s cache, or has been invalidated.

Implicit InvAck

The WriteBack a core in M sends in response to Invalidate. It carries the dirty data and simultaneously acknowledges the invalidation; no separate InvAck is sent (PL-CHAN-05).

M (Modified)

Line is dirty and held exclusively by one core: the only valid copy in the system; memory is stale.

MESI

Cache coherence model with four stable states: Modified, Exclusive, Shared, Invalid (see MESI State Transitions).

Nack

Negative acknowledgment: denies an Upgrade that lost a race. The only deniable request (PL-CHAN-04); the prescribed retry is ReadExclusive.

Outstanding transaction

A transaction whose completing response has not yet been received. A core may have at most one outstanding request per line (PL-CHAN-02), and its txn_id cannot be reused until completion (PL-TXN-01).

Requester

A core-side cache controller that initiates PicoLink transactions on channel A.

S (Shared)

Line is clean and may be held by multiple cores; memory also holds current data.

Serialization point

The property that the CM processes same-line transactions one at a time (PL-CM-03); the CM’s processing order defines the global coherence order of each line.

Silent transition

A requester state change that produces no message: E → M on a store, and S → I / E → I on clean eviction (PL-MESI-04). Silent transitions are why the directory over-approximates holders (PL-CM-02) and why an E directory entry means E-or-M (PL-CM-01).

txn_id

Transaction identifier. Core-initiated transactions use the core’s pool; CM-initiated Invalidate transactions use the CM’s pool; responses echo the identifier of the message they complete (see Transaction identifier rules).

Voluntary WriteBack

A WriteBack initiated by the core (capacity eviction of an M line), carrying a core-pool txn_id.